The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor and methods for forming a field-effect transistor.
Device structures for a field-effect transistor include a source, a drain, a channel region of semiconductor material arranged between the source and drain, and a gate structure including a gate electrode and a gate dielectric separating the gate electrode from the channel region. A gate voltage applied to the gate electrode is used to provide switching that selectively connects the source and drain to each other through the channel region.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a fin consisting of a solid unitary body of semiconductor material, heavily-doped source/drain regions formed in sections of the body, and a gate electrode that wraps about a channel located in the fin body between the source/drain regions. The arrangement between the gate structure and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state in comparison with planar transistors. This, in turn, enables the use of lower threshold voltages than in planar transistors, and results in improved performance and lowered power consumption.
When operating, a parasitic capacitance is inherently established between the conductive materials of the gate electrode and the source/drain regions. This parasitic capacitance may contribute to slower transistor turn-on and power loss. With scaling for advanced nodes, the parasitic capacitance increases in significance in device design.
Improved structures for a field-effect transistor and methods for forming a field-effect transistor are needed.